Course Description
The Universal Verification Methodology is the industry standard for functional verification of today's complex ASICs and FPGAs. Students will learn the content and use of UVM to architect and implement complex test benches. The characteristics and architecture of reusable verification components is a major focus of the course. Students will learn and implement verification components which are reusable across projects, from block level simulation to chip level simulation, and from simulation to emulation. The course projects teach and demonstrate advanced verification methodologies that prepare students for careers in functional verification of digital semiconductors.
DE Fee
Engineering Online GRAD
DE Program
MS E
FALL 2019
Classes Start:
August 21, 2019
Classes End:
December 6, 2019
Distance Education:
Yes
Class Type:
Lecture
Credits:
3.00
Delivery Method:
Internet
Restrictions:
ONLY distance-track students with grad standing in CN, CE, EE, or EPSE may register. All other students must request enrollment through the EOL Registration System (http://go.ncsu.edu/eol_registration).
