Course Description
Design of digital application specific integrated circuits (ASICs) and Field Programmable Gate Arrays (FPGAs) based on hardware description languages (Verilog) and CAD tools. Emphasis on design practices and underlying methods. Introduction to ASIC specific design issues including verification, design for test, low power design and interfacing with memories. Required design project. Expected Prior Experience or Background: ECE 310 is useful but not assumed. Functionally, I assume that students are familiar with logic design, including combinational logic gates, sequential logic gates, timing design, Finite State Machines, etc.
Fall 2025
Instructors
Meeting Patterns
Classes Start:
August 18, 2025
Classes End:
December 2, 2025
Location:
01103 James B Hunt Jr Centenni
Class Days:
M W
Class Start Time:
6:00pm
Class End Time:
7:15pm
Class Type:
Lecture
Credits:
3.00
Restrictions:
P: Grade of C or better in ECE 212 or equivalent. Requisite: EE or CPE Majors Only