Course Description
Architecture of microprocessors. Measuring performance. Instruction-set architectures. Memory hierarchies, including caches, prefetching, program transformations for optimizing caches, and virtual memory. Processor architecture, including pipelining, hazards, branch prediction, static and dynamic scheduling, instruction-level parallelism, superscalar, and VLIW. Major projects.
Type
Not all students present at each class meeting
Fall 2025
Instructors
Meeting Patterns
Classes Start:
August 18, 2025
Classes End:
December 2, 2025
Location:
01103 James B Hunt Jr Centenni
Class Days:
M W
Class Start Time:
10:15am
Class End Time:
11:30am
Class Type:
Lecture
Credits:
3.00
Restrictions:
Prerequisite: ECE 209 and ECE 212 Requisite: EE or CPE Majors Only