Course Description
Provide insight into current compiler designs dealing with present and future generations of high performance processors and embedded systems. Introduce basic concepts in scanning and parsing. Investigate in depth program representation, dataflow analysis, scalar optimization, memory disambiguation, and interprocedural optimizations. Examine hardware/software tade-offs in the design of high performance processors, in particular VLIW versus dynamically scheduled architectures. Investigate back-end code generation techniques related to instruction selection, instruction scheduling for local, cyclic and global acyclic code, and register allocation and its interactions with scheduling and optimization.
Type
Dual Level Course
Spring 2025
Instructors
Meeting Patterns
Classes Start:
January 6, 2025
Classes End:
April 22, 2025
Location:
02124 Engineering Building 3
Class Days:
M W
Class Start Time:
4:30pm
Class End Time:
5:45pm
Class Type:
Lecture
Credits:
3.00
Restrictions:
Prerequisite: ECE graduate students and ECE undergrads with a 3.5 or higher GPA
