Course Description
The Universal Verification Methodology is the industry standard for functional verification of today's complex ASICs and FPGAs. Students will learn the content and use of UVM to architect and implement complex test benches. The characteristics and architecture of reusable verification components is a major focus of the course. Students will learn and implement verification components which are reusable across projects, from block level simulation to chip level simulation, and from simulation to emulation. The course projects teach and demonstrate advanced verification methodologies that prepare students for careers in functional verification of digital semiconductors.
DE Fee
Engineering Online GRAD
DE Program
MS E
Fall 2024
Instructors
Meeting Patterns
Classes Start:
August 19, 2024
Classes End:
December 3, 2024
Distance Education:
Yes
Class Days:
[TBA]
Class Type:
Lecture
Credits:
3.00
Restrictions:
Enrollment for this course is through the Engineering Online Registration System. Go to http://go.ncsu.edu/eol_registration
