Course Description
Study of transaction-level modeling of digital systems-on-chip using SystemC. Simulation and analysis of performance in systems with distributed control. Synthesis of digital hardware from high-level descriptions. Physical design methodologies, including placement, routing, clock-tree insertion, timing, and power analysis. Significant project to design a core at system and physical levels. Knowledge of object-oriented programming with C and register-transfer-level design with verilog or VHDL is required.
Type
Not all students present at each class meeting
Fall 2024
Instructors
Meeting Patterns
Classes Start:
August 19, 2024
Classes End:
December 3, 2024
Location:
01230 Engineering Building 2
Class Days:
M W
Class Start Time:
8:30am
Class End Time:
9:45am
Classes Start:
August 19, 2024
Classes End:
December 3, 2024
Location:
Hybrid - Online and In-Person
Class Days:
[TBA]
Class Type:
Lecture
Credits:
3.00
Restrictions:
Restricted: ECE Graduate Students Only