ECE 564
ASIC and FPGA Design with Verilog
Section: 001

Course Description

Design of digital application specific integrated circuits (ASICs) and Field Programmable Gate Arrays (FPGAs) based on hardware description languages (Verilog) and CAD tools. Emphasis on design practices and underlying methods. Introduction to ASIC specific design issues including verification, design for test, low power design and interfacing with memories. Required design project. Expected Prior Experience or Background: ECE 310 is useful but not assumed. Functionally, I assume that students are familiar with logic design, including combinational logic gates, sequential logic gates, timing design, Finite State Machines, etc.

Fall 2024

Instructors

Meeting Patterns

Classes Start:
August 19, 2024
Classes End:
December 3, 2024
Location:
01103 James B Hunt Jr Centenni
Class Days:
M W
Class Start Time:
6:00pm
Class End Time:
7:15pm

Class Type:
Lecture
Credits:
3.00
Restrictions:
Prerequisite: ECE graduate students and ECE undergrads with a 3.5 or higher GPA

Tools

Panopto